The present invention relates to a semiconductor device. More particularly, it relates to a technology which is effective when applied to a semiconductor device having hetero-junction bipolar transistors (hereinafter referred to as HBTs) and to a radio communication device using the same.
In a HBT using different semiconductor materials for an emitter and a base (e.g., AlGaAs/GaAs, InGaP/GaAs, or the like), a collector current can be increased without lowering a current amplification factor since the leakage of holes into the emitter is suppressed by the barrier of the emitter-base junction thereof. In addition, a reduction in the film thickness of the base layer reduces the transit time of electrons and thereby allows an increase in the response speed of the transistor, i.e., the RF operation thereof.
Accordingly, the HBT has characteristics suitable for use in an RF (Radio Frequency) power amplifier, such as large current and RF operation. However, there is the possibility that a large base current may flow in the transistor due to heat variations and a local temperature rise to consequently increase a collector current and cause the defect that the emitter-collector junction breaks down. In spite of this, there has been a growing need for the miniaturization of a radio communication device (e.g., a mobile telephone or the like). Therefore, it has been required to scale down the semiconductor chip of a semiconductor device formed with the HBT, while suppressing an increase in the thermal resistance thereof.
Japanese Unexamined Patent Publication No. 2001-237319 (Patent Document 1) has a description on the layout of a semiconductor integrated circuit comprising an amplifier circuit consisting of a plurality of transistors arranged as a matrix on a single semiconductor chip. To suppress heat generation from the transistors, the layout divides the transistors into a plurality of groups by assigning a specified number of the transistors in the same row to one of the groups and equispacedly arranges the transistors in each of the groups. In this case, the spacing between the individual groups is adjusted to be larger than the spacing between the individual transistors in each of the groups.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2001-237319